Proposal Defense
Transcript: OPTIMIZATION OF GRAPHENE FIELD-EFFECT TRANSISTOR (GFET) USING TAGUCHI-BASED GREY RELATIONAL ANAYLSIS (GRA) MUHAMMAD ARIFF AFFIAN BIN CHE LAH B021410235 DR FAUZIYAH BINTI SALEHUDDIN 1 This project is about a new bilayer graphene field-effect (Bi-GFET) design that will be proposed to replace the older version of MOSFET’s layout. Meanwhile, in order to achieve the higher on-current (ION) characteristics, new metal gate/high-k dia-electric will be chose to replace the conventional poly-silicon/SiO2. Taguchi-based grey relational analysis (GRA) method will be applied as optimization methods for variety of propose parameters. These parameters must achieve the most optimum value that accepted by Low Power (LP) technology by International Technology Roadmap for Semiconductor (ITRS). INTRODUCTION ORIGINAL VERSION ORIGINAL VERSION Bi-GRAPHENE LAYOUT Bi-GRAPHENE LAYOUT OBJECTIVES 2 #1 The main goal of this research is to optimize the grapheme field-effect transistor (GFET) device using Taguchi-based grey relational analysis (GRA). The objectives are specific: #2 1) To design MOSFET-like GFET by using ATHENA and ATLAS modus of SILVACO software. #3 2) To obtain and analyze the most optimum value of process parameters of Bi-GFET that meet the requirement of low power (LP) technology by International Technology Roadmap Semiconductor (ITRS) SCOPE OF WORK This project execution is based on simulation and parameters measurement. The traditional MOSFET’s layout will be replaced with bilayer graphene FET (Bi-FET). Metal gate/high-k dia-electrics will be used to change the conventional poly-silicon/SiO2. The fabrication of the graphene field-effect transistor (GFET) will be done by using ATHENA module in SILVACO’s TCAD tool. Meanwhile, ATLAS module in SILVACO’s TCAD will be used to measure all parameters and electrical characteristics. Meanwhile, Taguchi-based (GRA) will be optimization method for all the parameters and will be applied to obtain the most optimum parameters of Bi-GFET. PROBLEM STATEMENT Based on Moore’s Law, number of transistors per square inch on integrated circuits had doubled every year since their invention and suggests exponential growth is unlikely to continue. These are because there are many limitations in the transistor to overcome such as silicon transistors can age and fail. Transistors also have limited power-handling capabilities. To propose layout with better efficiency, low power consumption and high on-current, a brand new layout is propose. A lot of experiments are conducted to search variation of new design and materials to likely overcome these limitations. PROJECT SIGNIFICANCE Graphene FET can be used as detector of ionizing radiation due to the sensitivity of graphene to ionization-induced local electric field perturbations. Graphene also widely implement in electronic applications. Transparent conductor application also optimizing graphene FET in their used. REFERENCE [1] Shintaro Sato, “Application of graphene to electronics device”, Active-Matrix Flatpunel Displays and Device (AM-FPD), 2017 24th International Workshop, 2017. [2] Pierre-Antoine Haddad, Denis Flandre and Jean-Pierre Raskin, “A Quasi-Static Model of Silicon Substrate effect in Graphene field effect transistors’, IEEE Electron Device Letters, vol 38, issue 7, pp. 987-990, July 2017. [3] Renyan Jiang and Xing Yao, “A response-based method for analyzing data from Taguchi experiments”, Second International Conference on Reliability System Engineering (ICRSE), pp. 1-6, 2017. [4] R. Stanley Williams, “What’s Next? [ The End of the Moore’s Law] “, Computing in Science and Engineering, vol 19, issue 2, pp. 7-13, 2017. [5] Li D. and Kaner R.B, “Graphene-Based Materials”, Material Science, vol 320, pp. 1170-1171, 2008. ? Question Time? Thank Your Audience! Goodbye Now!